Sr Staff FAE, RTL to GDS Implementation

We are seeking a Sr Staff FAE, RTL to GDS Implementation to join our team in Bengaluru, India.

You have spent years building expertise in physical design, and you know that the difference between a chip that tapes out on schedule and one that slips by a quarter usually comes down to a methodology decision made during floorplanning or a timing bottleneck nobody caught until route.

As a Sr Staff FAE, RTL to GDS Implementation, you will:

• Deploy Fusion Compiler and ICC2 on customer designs at advanced nodes (5nm, 3nm, and beyond), solving complex PPA challenges using machine learning placement, physical synthesis, and multi-source CTS techniques
• Work directly with customers to develop, debug, and optimize RTL to GDS implementation flows, identifying design bottlenecks and tool behavior that blocks timing closure or violates power budgets
• Run competitive benchmarks to demonstrate Synopsys implementation solutions against rival tools, documenting QoR improvements and building the technical narrative that wins customer evaluations and displaces competition
• Translate customer findings into clear, actionable requirements for Synopsys R&D, driving tool enhancements that solve both immediate design challenges and long-term methodology gaps across the customer base
• Lead customer migration to new EDA tool versions by validating flows, identifying regressions, ensuring PPA gains carry through to production designs, and building confidence in adoption
• Act as the technical bridge between customers and Synopsys R&D, representing customer needs internally with credibility and representing product capabilities externally with authority
• Proactively identify recurring customer pain points across engagements and develop reusable solutions, scripts, or methodologies that scale beyond a single design or customer and influence product direction

Requirements:

• 10+ years of hands-on ASIC design or application engineering experience, with deep expertise in physical implementation including placement, optimization, CTS, and routing
• Expert-level knowledge of Synopsys backend tools, specifically Fusion Compiler and ICC2, including logical and physical synthesis, timing closure techniques, macro placement, and routing at advanced nodes
• Strong working knowledge of RTL to GDS full flow, with the ability to debug issues anywhere from synthesis through signoff and articulate root cause to both customers and R&D
• Demonstrated experience working directly with customers or cross-functional engineering teams to solve complex technical problems under tight schedules and high stakes
• Deep understanding of advanced node design challenges (5nm and below) and the methodologies required to achieve timing, power, and area targets at scale

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.