Description
The Silicon One team at Cisco is looking for an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.
You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
Key responsibilities include:
- Crafting groundbreaking next-generation networking chips
- Leading the DFT and quality process through the entire Implementation flow and post-silicon validation phases
- Working with ATE engineers on pattern translation and validation
Requirements:
- Bachelor’s degree in Electrical or Computer engineering and 8+ years of experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of experience
- Prior experience with ATPG and EDA tools like TestMax or Tetramax or Tessent or similar tool sets
- Prior experience working with Gate level simulation, including timing-based simulations with SDF, debugging with VCS and other simulators
- Prior post-silicon validation and debug experience
- Prior experience with scan insertion
Preferred qualifications:
- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
- Prior experience with EDA tools like Tessent
- Prior experience with Jtag protocols (p1500, p1687)
- Prior experience with SSN
- Scripting skills: Tcl, Python/Perl
- Prior experience with test static timing analysis constraints development and timing closure
Benefits:
- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- Paid time away (vacation, holidays, sick time)
- Opportunities for professional growth and development