Description
We are seeking a highly motivated FPGA Design Engineer with experience developing high-performance digital designs.
The ideal candidate will be responsible for designing, implementing, verifying, and debugging FPGA-based solutions for complex avionics solutions for cutting-edge Unmanned Aerial Vehicles (UAV).
Responsibilities:
- Design and develop FPGA-based communication modules for advanced UAV platforms.
- Develop solutions that enable precise timing synchronization and redundancy across flight controllers.
- Integrate FPGA solutions with system-level architecture in collaboration with cross-functional engineering teams.
- Perform synthesis, implementation, timing closure, bitstream generation.
- Debug, test, and optimize for reliability, latency, and throughput.
- Collaborate with PCB designers during board bring-up and hardware validation.
- Contribute to FPGA architecture discussions and help define long-term technical direction within the platform.
- Participate in design reviews and maintain engineering documentation.
Requirements:
- B.S., M.S, PhD degree in Electrical Engineering, Computer Engineering or STEM (Science, Technology, Engineering, or Mathematics) discipline, such as Aerospace, Mechanical, or Electrical Engineering.
- Strong experience with FPGA design, implementation, and verification using VHDL or SystemVerilog.
- Demonstrated ability to build reliable, high-performance digital communication systems.
- Solid understanding of timing closure, clock domain crossing, and system-level integration.
- Comfortable working in a fast-paced, collaborative environment with evolving requirements.
- Strong debugging and problem-solving skills.
- Knowledge of FPGA timing analysis and timing closure techniques.
- Familiarity with version control tools such as Git.
Preferred Qualifications:
- Experience with Xilinx FPGA ecosystem (Vivado, toolchains, etc).
- In-depth understanding of ethernet and network stack implementation.
- Experience developing flight computers.
- Experience designing solutions for safety-critical real-time systems.
- Experience with AXI4, AXI-Stream, and memory-mapped interfaces.
- Experience using TCL scripting to automate FPGA build flows.
- Knowledge of CI/CD practices for FPGA development.
Additional Information:
Full-time regular employee offer package: Pay within range listed + Bonus + Benefits + Equity. Temporary employee offer package: Pay within range listed above + temporary benefits package (applicable after 60 days of employment).