Serdes IP Design Engineer

We are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow to join our team of experienced mixed-signal design and verification engineers. The successful candidate will work on high-speed SERDES products, including USB4.0v2, USB4.0, PCIe4.0, Ethernet, DP2.0, HDMI2.1, and MIPI MPHY products up to 40 Gbps.

Key Responsibilities

• Design and develop cutting-edge semiconductor solutions
• Work on intricate tasks such as chip architecture, circuit design, and verification
• Collaborate with a professional team of digital and mixed-signal engineers
• Develop high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips

Requirements

• MSEE graduate or BSEE plus minimum 3 years of digital design and verification experience in the industry
• Good experience in writing block-level test-cases including constrained directed random tests
• Familiarity with Verilog and VCS
• Knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
• Scripting experience in Shell, Perl, Python, and TCL is a plus
• Good theoretical and practical understanding of digital signal processing and data recovery circuits
• Good communication skills for interacting between different design groups and customer support teams

Preferred Experience

• RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog
• Defining synthesis design constraints and resolving STA issues
• Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
• Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols
• Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams

Benefits

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP, allowing purchase of Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country
• Competitive salaries