SerDes Analog & DSP System, Architect

We are seeking a visionary and detail-oriented architect to lead the design and development of SerDes IP for PAM4 transceivers targeting PCIe and Ethernet applications.

As a SerDes Analog & DSP System Architect at Synopsys, you will own the architecture of SerDes IP, interpret SerDes standards, develop system models and link budgets, and lead the design of analog macro-level circuits.

Your responsibilities will include:

• Developing and implementing SerDes IP for PAM4 transceivers
• Designing and verifying analog and DSP components
• Leading a team of engineers and collaborating with cross-functional teams
• Developing and presenting technical insights to peers and customers
• Mentoring junior engineers and contributing to the company's talent pipeline

The ideal candidate will have:

• PhD or MSc with 10+ years of experience in SerDes/high-speed analog and mixed-signal design
• Silicon-proven, transistor-level design experience in TX, RX, and clock paths within SerDes architectures
• In-depth knowledge of SerDes sub-circuits and DSP/communications theory
• Strong experience with EDA tools, SPICE simulators, and programming languages such as Verilog-A, SystemVerilog, C, TCL, and Python

We offer a comprehensive range of health, wellness, and financial benefits, including competitive salaries, bonuses, and equity.