RTL Design - Senior to Principle Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years building RTL that actually ships, not just passes simulation. The kind of RTL that holds up under post-silicon scrutiny when customers are integrating your IP into their SoC and every timing path matters. You know that a well-written micro-architecture spec is not documentation for the sake of it, it is the contract between what the protocol demands and what your design delivers.

You will:

• Design and develop high-speed mixed-signal PHY IP blocks in SystemVerilog and Verilog as part of a cross-functional digital design team
• Author detailed micro-architecture specifications based on industry protocol standards, translating requirements into implementable design decisions
• Execute RTL design from concept through tape-out, ensuring design quality through Linting, CDC checks, and adherence to coding standards
• Collaborate with verification engineers to debug and resolve issues in RTL simulations and gate-level simulations with SDF timing annotation
• Provide technical support to customers during SoC integration, post-silicon bring-up, and field deployment
• Participate in design reviews and mentor junior engineers on RTL best practices

Your RTL designs will power high-speed connectivity IP used in customer SoCs across automotive, mobile, and data center applications. The micro-architecture decisions you make today will determine whether customer integrations succeed on schedule or require costly respins.

Requirements:

• 5+ years of hands-on experience in ASIC RTL design flow, from specification through tape-out
• Strong proficiency in SystemVerilog and Verilog for complex digital design
• Experience with scripting languages such as Python, Perl, or Tcl for design automation
• Solid understanding of design quality checks including Linting, CDC analysis, and synthesis constraints
• Strong English communication skills for cross-functional collaboration and customer interaction
• Experience with post-silicon debugging and customer support is a strong plus
• Knowledge of high-speed serial protocols, DFT techniques, or UVM verification methodologies is a plus

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.