ASIC Design for Test Engineer

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

You will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle.

Responsibilities:

• Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
• Create and enhance automation scripts to improve implementation robustness and efficiency.
• Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
• Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.

Minimum Qualifications:

• A Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months).
• Qualifying education should be in ASIC DFT or a related field.
• Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (Built-In Self-Test, including memory BIST and boundary scan).
• Familiarity or introductory hands-on exposure to EDA and ATPG tools along with scripting or coding skills in Python, Tcl, or Perl.
• Experience working with gate-level simulations and debugging using simulators like VCS.

Preferred Qualifications:

• Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation.
• Understanding of basic VLSI circuit physical behaviors in silicon (such as electromigration and temperature/voltage variation effects) and familiarity with basic timing concepts (setup/hold times, metastability).
• Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
• Strong verbal and written communication skills to collaborate effectively with frontend RTL, backend physical design, and verification teams.

Benefits:

• Medical, dental and vision insurance
• 401(k) plan with a Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness
• Non-exempt employees receive 16 days of paid vacation time per full calendar year
• Exempt employees participate in Cisco’s flexible vacation time off program
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• Optional 10 paid days per full calendar year to volunteer