Description
We are looking for a Senior Mask Layout Design Engineer to join our growing team of diverse individuals responsible for contributing to our latest generation chiplet interface projects.
Job Description: As a Senior Mask Layout Design Engineer, you will perform physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. You will work closely with mixed-signal design engineers to customize designs for integration in VLSI products. Your responsibilities will also include taking part in floor planning, custom layout and verifying against design rules and schematics.
Requirements:
- Have a BSEE or equivalent experience
- Minimum of 5+ years industry experience in Mask and Layout Design
- Deep understanding and previous experience with FinFET technology
- Expertise with Cadence custom circuit design tools, particularly Virtuoso
- Ability to handle fast-paced projects and iterate quickly based on designer's feedback
- Effective teamwork and communication skills
- Scripting languages like Perl, Python, Skill etc. is a plus
- Knowledge of DRC and LVS checking flows, ability to customize decks