Senior IP Design Verification Engineer - XBAR IP

NVIDIA is seeking a Senior Verification Engineer to verify the design and implementation of next-generation memory subsystem units for leading GPUs and SOCs. This role offers the opportunity to make a real impact in a dynamic, technology-focused company.

The GPU initially simulated human imagination for video games and films, but now NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars.

Responsibilities:

• Verify the ASIC design, architecture, and micro-architecture of memory sub-systems/units using advanced verification methodologies.
• Understand the design and implementation, define the verification scope, develop the verification infrastructure, and verify the correctness of the design.
• Create test plans, tests, and verification infrastructure for complex IPs/sub-systems.
• Build reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven verification methodology.
• Work on advanced verification methodologies like SV/UVM.
• Perform functional coverage-driven verification closure.
• Collaborate with architects, designers, and pre- and post-silicon verification teams.

Requirements:

• B.Tech./M.Tech., or equivalent experience.
• 4+ years of relevant experience.
• Experience in verification of complex IPs/units and sub-systems.
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
• Expertise in Verilog.
• Knowledge in SystemVerilog or similar HVL/UVM or VMM.

Preferred Qualifications:

• Experience in memory subsystem or network interconnect IP verification.
• Debugging and analytical skills with sound scripting knowledge.
• Good communication and excellent team player.