ASIC Digital Design, Manager

Synopsys is seeking a Senior Staff ASIC Digital Design Engineer to join their LPDDR PHY IP team. The successful candidate will contribute to all phases of DDR PHY IP design, from specification to productization, and provide customer support.

Responsibilities:

• Design and micro-architect LPDDR PHY IP, writing Verilog and SystemVerilog code and design specifications
• Conduct simulation and analysis of designs, working with Verification, Timing, DFT, and Power teams
• Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues
• Maintain and improve design automation flow and processes

Requirements:

• BS in Electrical Engineering
• Minimum 8 years of experience in complex technical development
• Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation
• Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
• Excellent communication skills and self-motivation
• Understanding of memory and memory PHY architecture is a plus

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP, allowing purchase of Synopsys common stock at a 15% discount
• Retirement plans, varying by region and country
• Competitive salaries