DFT-Timing Engineer

Join NVIDIA's dynamic team as a DFT-Timing Engineer. You'll drive timing analysis and closure for DFT logic on NVIDIA chips, including GPUs, CPUs, DPUs, LPUs, and SoCs. Collaboration with various teams will be essential to develop timing closure strategies, create timing constraints, and implement ECOs.

Key Responsibilities:

• Drive timing analysis and closure for DFT logic across all hierarchical levels
• Develop timing constraints for custom DFT designs and drive timing and power convergence
• Implement ECOs and continuously improve workflows and designs through automation, resilience, and standardization

Requirements:

• BS or equivalent in Electrical or Computer Engineering with 5+ years' experience, or MS with 2+ years' experience
• Hands-on experience in Static Timing Analysis (STA) and driving timing convergence
• Expertise in analysis and fixing of timing paths through ECOs and developing timing constraints
• In-depth knowledge of industry-standard timing convergence tools

Preferred Qualifications:

• Understanding of DFT logic and experience with DFT timing closure
• Background in domain-specific STA and timing convergence
• Experience in methodology and/or workflow development

Compensation: Your base salary will be determined based on your location, experience, and other objective job-related factors. Expected base salary ranges are 136,000 USD – 218,500 USD for Level 3 and 168,000 USD – 264,500 USD for Level 4. You will also be eligible for equity and benefits.