Description
NVIDIA's Silicon Co-Design Group is seeking an HSIO Validation Engineer to characterize and qualify high-speed I/Os on brand-new silicon serving datacenter, AI, and client markets.
The ideal candidate will own end-to-end characterization and validation of high-speed IO, including PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet.
Key responsibilities:
- Develop and execute validation test plans for silicon and SoC-level HSIO features
- Drive power characterization and optimization across IO interconnects under workload-representative stimuli
- Drive systematic root-cause analysis for complex HSIO bugs
- Assess manufacturing and yield implications of HSIO margin distributions
- Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure
Requirements:
- BS or MS in Electrical or Computer Engineering (or equivalent), with 6+ years in post-silicon HSIO validation, characterization, or a closely related discipline
- Deep understanding of high-speed serial link protocols and SERDES architecture
- Strong SI and PI fundamentals, with validation experience across silicon and platform boundaries
- Hands-on with lab instrumentation and Python-based test automation
Preferred skills:
- Hands-on experience with PCIe Gen5/Gen6 or NVLink validation on production silicon
- Prior SERDES, mixed-signal, or analog circuit design experience
- Track record of translating rack-environment conditions into silicon/board characterization
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