ASIC Engineer

NVIDIA's Global Flows Team advances RTL quality and sign-off methodologies used across NVIDIA CPU programs. As an ASIC Engineer, you will develop and deploy innovative RTL design-quality methodologies, including CDC, RDC, Netlist/Design Auditors, Power Insertion, lint, and related structural checks.

Your role will involve:

• Analyzing flow results in the context of design intent and identifying root causes across RTL, constraints, tools, and methodology.
• Establishing quality requirements and readiness criteria for project achievements while monitoring regressions, violation trends, and sign-off status.
• Collaborating across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
• Assessing new tool releases and methodology capabilities, coordinating their integration into project environments.
• Improving runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and engineering guidelines.

We are seeking a professional with:

• A Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 3+ years of proven experience in ASIC or SoC RTL design or design-methodology.
• Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
• Knowledge of digital design and microarchitecture, including pipelines, finite-state machines, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
• The ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.
• Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.