IP Verification- Staff Engineer

You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You will specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. You will develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. You will design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. You will perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. You will collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. You will leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. You will contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: You will ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. You will drive innovation in verification methodologies, setting new standards for efficiency and coverage. You will enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. You will strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. You will mentor and support junior engineers, fostering a culture of learning and continuous improvement. You will contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.