Description
Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture.
As a Senior RTL Design Engineer, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing complex chips.
Your Impact
This role offers a unique chance to shape the future of networking innovation within Cisco Silicon One.
- Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification.
- Sub-system/SoC integration and verification.
- Review/enhancement of RTL codes.
- Improve flows and methodologies to streamline IP/SoC development and integration.
- Work closely with the verification team for complex debugs to resolve verification failures.
- Close interaction with the physical design team to reach better physical design QoR.
Minimum Qualifications
- 6+ years of industry experience in ASIC digital design.
- Proficient in Verilog/System Verilog coding.
- Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
- Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.
- Ability to write scripts using Python, Tcl, Make.
Benefits
No benefits mentioned.