LPDDR IP Design Engineer

We are looking for a Staff ASIC Digital Verification Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution.

Responsibilities:

• Defining and tracking Verification test plans
• Designing and writing constrained-random SystemVerilog testbenches using UVM
• Writing SystemVerilog assertions
• Writing functional coverage
• Debugging RTL and GLS failures
• Code coverage Analysis
• Providing mentoring and guidance to less experienced team members

Required Skills:

• BSEE in EE with 5+ years of industry experience
• Digital verification in UVM environment, Formal Verification is a plus
• Understanding of memory and memory PHY architecture
• Knowledge of DFI, Memory Controller or Memory Subsystem
• Verilog, System Verilog and Perl/Python scripting skills
• Debugging skills
• Demonstrates good communication and problem-solving skills
• Understanding of high-speed interface protocols is a plus

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries