Description
NVIDIA is looking for RTL Design Engineers for its High Speed IO IP's deployed in Automotive chips.
As a designer, you will be responsible for understanding specific protocol concepts and features, making architectural trade-offs based on feature/performance/power requirements, analyzing system implications, coming up with the micro-architecture, implementing RTL, driving verification, closing timing, and supporting silicon validation.
Responsibilities:
- Own micro-architecture and RTL development of design modules
- Micro-architect features to meet performance, power, and area requirements
- Work with HW architects to define critical features
- Partner with verification teams to verify the correctness of implemented features
- Collaborate with timing, VLSI, and Physical design teams to ensure design meets timing, interface requirements, and is routable.
Requirements:
- BTech/MTech in EE, ECE, or similar stream
- 2+ years of experience in crafting complex Units and CPU/micro-controller-based Sub-systems
- Knowledge of HSIO standards, protocols, and architectures of modern SOC's would be a significant plus
- Excellent influencing skills resulting in collaboration with cross-cultural, multi-geography, and matrixed teams
- Good debugging, analytical, and problem-solving skills
- Great interpersonal skills and ability to work as an excellent teammate
- Working exposure with AI tools like Claude and Cursor would be a plus
NVIDIA offers highly competitive salaries and a comprehensive benefits package.