Description
NVIDIA is seeking a motivated ASIC Timing Engineer to join its dynamic team. The engineer will drive physical design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs, and SoCs at various levels.
Responsibilities:
- Drive physical design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and/or full chip level.
- Help drive frontend and backend implementation, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
- Play a pivotal role in the success of innovative projects and advancement of NVIDIA's technology, working in a cross-functional environment interacting with multiple teams.
Requirements:
- Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
- Proficiency in Timing and Static Timing Analysis (STA).
- Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.
- Expertise with industry standard EDA and timing convergence tools.
Preferred qualifications:
- Proven experience in timing convergence for ASICs, CPUs, GPUs, or Network processors.
- Knowledge of deep sub-micron process nodes.
- Proficiency in AI/LLM and programming languages.
- Experience in physical design and optimization (e.g., synthesis, floorplanning, placement, CTS, routing, power) is a plus.
NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity and benefits.