You are a senior DFT architect with deep experience developing and deploying test solutions for complex ASIC and SoC designs.

You will drive advanced DFT methodologies for complex ASIC and SoC programs across customer and internal engagements.

Key responsibilities include:

Serving as a senior technical expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions
Leading deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies
Architecting scalable test access and instrumentation networks using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards
Developing best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization
Driving reusable methodologies, automation, and signoff criteria that improve deployment quality and engineering efficiency

The impact you will have:

Enabling successful deployment of advanced DFT methodologies across some of the most complex semiconductor programs in the industry
Improving test quality, manufacturability, and silicon reliability for strategic customers
Influencing TestMAX methodology adoption through technical leadership and trusted customer engagement

Requirements:

BS/MS in Electrical Engineering, Computer Engineering, or a related field
18+ years of experience in the semiconductor or EDA industry, including deep experience in DFT, ATPG, and manufacturing test methodologies
Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs
Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions

Benefits:

Digital CAD DFT Methodology, Sr Architect

Skills