Description
ASIC Design Verification Engineer specializing in Simulation & Emulation is required at Cisco. The successful candidate will develop and execute verification strategies to ensure correctness and performance of complex hardware designs, focusing on emulation platforms.
Your Impact As a Design Verification Engineer, you will be responsible for:
- Developing and implementing verification plans and test benches using emulation tools and methodologies.
- Collaborating with design and validation teams to identify verification requirements and coverage goals.
- Utilizing emulation platforms to run large-scale verification tests and debug design issues.
- Analysing verification results, identifying bugs, and working closely with design engineers to resolve issues.
- Maintaining and enhancing verification infrastructure and automation frameworks.
- Documenting verification processes, test cases, and results to ensure traceability and reproducibility.
- Staying current with emerging verification technologies and best practices, particularly in emulation.
- Mentoring junior engineers and contributing to team knowledge sharing.
Minimum Qualifications:
- Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
- Strong experience in Design verification methodologies using UVM or OVM
- Relevant experience in design verification with a strong emphasis on Test Methodologies
- Exposure to Emulation Tools like Cadence Palladium, Synopsys Zebu, etc.
- Experience in Networking (Ethernet, AXI, AMBA, PCIe, etc.)