Senior Staff Digital Methodology Engineer - Design for Testability (DFT)

You will work on methodologies that define how the world's most complex chips get tested. The problems are hard, the customers are sophisticated, and what you build will matter.

As a Senior Staff Digital Methodology Engineer - Design for Testability (DFT), you have spent over a decade architecting test solutions for chips that power everything from autonomous vehicles to data centers. You understand that DFT is not an afterthought, it is the difference between a design that ships on time and one that bleeds money in yield loss.

Responsibilities

• Define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs, translating architecture decisions into deployable best practices
• Lead deployment of advanced test solutions including scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation networks, and embedded test IP across multi-billion-gate designs
• Architect scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards for complex multi-die and chiplet-based systems
• Develop automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl that accelerate adoption across business units
• Serve as technical leader and subject matter expert for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements and internal escalations
• Collaborate directly with R&D teams to influence TestMAX product roadmap based on real deployment challenges and customer requirements
• Provide technical leadership for strategic customer engagements, methodology reviews, and complex DFT architecture decisions that impact tapeout schedules and silicon success

The Impact You Will Have

• Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs in AI, automotive, and hyperscale computing
• Drive measurable improvements in test coverage, pattern count reduction, and manufacturing yield through methodology standardization and best-practice development
• Influence next-generation TestMAX capabilities by translating customer deployment challenges into product requirements that shape future releases
• Accelerate adoption of standards-based test architectures across strategic accounts, reducing time-to-market and improving silicon reliability
• Improve engineering productivity across multiple programs through automation frameworks and reusable methodology packages that eliminate redundant work
• Establish Synopsys as the trusted technical advisor in DFT and manufacturing test, strengthening customer relationships and competitive positioning
• Contribute to breakthrough technologies powering autonomous vehicles, AI accelerators, and next-generation networking infrastructure

Requirements

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
• 10+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies
• Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs, including successful tapeouts
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments
• Deep technical knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, stuck-at/transition/path-delay/bridge/cell-aware fault models, and coverage optimization techniques
• Expertise deploying IEEE 1149.1 (JTAG), IEEE 1149.6 (AC JTAG), IEEE 1687 (IJTAG), and IEEE 1500 standards in complex test access architectures
• Experience integrating DFT IP including Codec/embedded compression, OCC, LBIST, TAP controllers, JTAG and IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers
• Strong understanding of RTL-to-GDSII flows and how DFT interacts with synthesis, physical design, timing closure, and signoff
• Proficiency with Tcl, Python, Perl, or Shell scripting for methodology automation and deployment
• Experience defining enterprise-wide DFT standards and signoff methodologies is a strong plus
• Background supporting advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, or yield improvement is highly valued
• Knowledge of functional safety standards and automotive test requirements is a plus
• Contributions to industry test standards, technical publications, patents, or conference presentations strengthen your candidacy

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries