Senior Design Verification Engineer - Interconnect IP

As a Senior Design Verification Engineer at NVIDIA, you will be responsible for verifying the ASIC design, architecture, and micro-architecture of the GPU memory subsystem unit using advanced verification methodologies.

Your key responsibilities will include:

• Defining the verification scope and developing the verification infrastructure
• Creating test plans, tests, and verification infrastructure for complex IPs/sub-systems
• Performing performance and deadlock verification of the GPU memory subsystem unit
• Building reusable bus functional models, monitors, checkers, and scoreboards
• Conducting functional coverage-driven verification closure
• Collaborating with architects, designers, and pre- and post-silicon verification teams

To be successful in this role, you will need:

• A Master's degree or equivalent experience in Electrical/Computer Engineering or a related field
• 5+ years of ASIC design verification experience on complex IPs, units, or sub-systems
• Deep understanding of verification methodologies and languages, including Verilog, SystemVerilog, and UVM
• Hands-on experience across the full verification flow
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Exposure to industry-standard verification tools for simulation and debug

Experience in memory subsystem or network interconnect IP verification, as well as familiarity with AI techniques to improve verification workflows, would be a plus.