IP Manager

We are looking for an IP Manager to join NVIDIA's Networking front-end design team. In this role, you will lead and manage a cluster of IP teams responsible for both design and design verification (DV) of complex hardware IP blocks across NVIDIA's next-generation SmartNIC and DPU products.

You will own the end-to-end delivery of IPs , from micro-architecture definition and RTL implementation through functional verification, lint/CDC/RDC closure, synthesis, and silicon readiness.

Responsibilities

• Lead, mentor, and grow a team of design and verification engineers across a cluster of IP blocks. You will define team structure, hiring plans, and career development paths to build a strong, scalable organization.
• Own the end-to-end execution of IP delivery , micro-architecture, RTL design, functional verification, coverage closure, assertions, formal verification, and synthesis handoff. You will set quality bars, review schedules, and drive milestone adherence across your IP cluster.
• Define and drive verification strategies, test plans, coverage goals, and sign-off criteria for your IPs. Your team will develop UVM-based constrained-random and directed test environments, achieve functional and code coverage targets, and ensure robust regression infrastructure.
• Partner with architecture, SoC integration, physical design, DFT, firmware, and software teams to resolve cross-functional dependencies, close interface specifications, and ensure seamless IP integration.
• Establish and improve design and verification methodologies, best practices, reuse strategies, and automation flows to increase team productivity and IP quality across tape-outs.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 10+ years of experience in ASIC/SoC design or verification, including 2+ years in a people management or technical leadership role managing multi-engineer teams.
• Strong understanding of digital design fundamentals , RTL coding (Verilog/SystemVerilog), micro-architecture, timing, clocking, reset, power management, and synthesis constraints.
• Strong understanding of verification methodologies , e-specman/UVM, constrained-random verification, coverage-driven verification, assertions (SVA), and formal verification techniques.
• Experience managing IP delivery across the full lifecycle , specification, design, verification, synthesis handoff, and post-silicon support.
• Demonstrated ability to manage multiple IPs or projects in parallel, balancing resources, schedules, and quality trade-offs.
• Experience with EDA tools for simulation, lint, CDC, RDC, synthesis, and debug.
• Ability to communicate technical status, risks, and trade-offs clearly to engineering leadership and cross-functional partners.

Nice to Have

• Experience with high-speed interfaces such as PCIe, NVLink, HBM, DDR, or high-speed SerDes IP blocks.
• Experience building or scaling verification infrastructure , regression frameworks, coverage automation, CI/CD pipelines for hardware, or emulation/FPGA prototyping flows.
• Hands-on experience with scripting and automation using Python, Perl, TCL, or shell scripting to improve team workflows.
• Background in GPU, networking, or AI/HPC-related IP domains is a strong plus.