Description
Join Cisco's CHG Team in Armenia, a team at the forefront of physical design for the globally recognized Silicon One brand.
Lead the end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out to ensure production-ready design delivery. Apply deep expertise in synthesis, place-and-route, and timing closure to meet stringent performance, power, and area (PPA) goals. Collaborate with global frontend, IP, and CAD teams to resolve complex implementation challenges and ensure seamless system-level integration. Advance physical design methodologies by leading technical investigations and proposing improvements to streamline development flows. Provide technical direction to peers to foster an innovative engineering environment that delivers impactful networking solutions.
Minimum Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
- Minimum of 8 years of experience in ASIC design, physical implementation, and verification.
- Proven expertise in deep submicron CMOS technologies.
- Extensive knowledge of the full design cycle from RTL to GDSII.
- Demonstrated mastery in block-level synthesis, place-and-route, and timing closure.
- Excellent verbal and written communication skills in English.
Preferred Qualifications:
- Direct experience with EM/IR and ESD analysis, including debugging and solution development.
- Proficiency in scripting languages such as Tcl, Python, or Shell to improve design flow efficiency.
- Proven ability to mentor team members and foster a collaborative environment.
- Experience collaborating with global teams and external vendor partners.