Sr Staff Applications Engineer, Simulation & Debug

You will work as a Sr Staff Applications Engineer, Simulation & Debug at Synopsys, driving customer deployments of VCS and Verdi simulation and debug platforms.

You have spent years in verification, thinking like both designers and engineers, and understand the importance of simulation beyond just running tests.

Your responsibilities include:

• Driving customer deployments of VCS and Verdi simulation and debug platforms
• Diagnosing complex technical issues across UVM testbenches and gate-level simulations
• Leading competitive engagements and benchmarking efforts
• Collaborating with R&D and product teams to gather customer requirements
• Developing and optimizing automation scripts in Perl, Python, TCL, Shell, and Make
• Interfacing across global teams to propose solutions and drive product improvements
• Supporting customers through technical escalations

This role requires:

• Bachelor's or Master's in Electronics Engineering or equivalent
• 5-12 years of hands-on experience in verification or application engineering
• Deep expertise in simulation technologies, UVM, SystemVerilog Assertions (SVA), and verification methodologies
• Strong command of HDL languages including Verilog, VHDL, and SystemVerilog
• Proven experience with gate-level simulation, timing-aware verification, and low power flows using UPF
• Advanced scripting ability in Perl, Python, TCL, Shell, and Make

You will have the opportunity to enable customers to close verification faster, influence the VCS and Verdi product roadmap, win competitive deals, and accelerate adoption of advanced features.

Rewards and benefits include a comprehensive range of health, wellness, and financial benefits.