ASIC Digital Design, Sr Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years building RTL that tapes out clean, not almost clean, actually clean, and you know the difference between a subsystem that works in simulation and one that survives silicon. The dopamine rush you get from first-time-right RTL is real, and it is what keeps you coming back to the hardest parts of digital design. You have driven multiple tape-outs and learned that the architecture decisions you make in week two will either save or sink the team in month six. You think in hierarchies, timing paths, and power domains without losing sight of what the block is actually supposed to do. Working with verification teams does not slow you down, it sharpens your thinking, and you write RTL that makes their job possible, not harder.

Responsibilities

• Own the full lifecycle of complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff, and final release
• Craft subsystem architecture and functional specifications, define micro-architecture, and write production-quality RTL using industry best practices
• Drive RTL quality checks including lint, CDC, RDC, and work closely with verification teams to ensure functional correctness and coverage closure
• Integrate and design around standard protocols including PCIe, DDR, UFS, USB, and AMBA-based interconnects
• Implement low power design techniques across clock gating, power gating, and multi-voltage domains, ensuring power intent is captured and verified
• Collaborate with logic synthesis, STA, and physical design teams to ensure timing closure, develop synthesis constraints, and resolve equivalence check issues
• Work with DFT teams to architect scan, MBIST, and other testability features into your subsystems from the start

The Impact You Will Have

• Your RTL will tape out in production silicon used by leading semiconductor companies building next-generation AI, automotive, and mobile SoCs
• The subsystems you architect will enable faster time-to-market for Synopsys IP customers who depend on proven, reusable, and robust design blocks
• Your attention to RTL quality and first-time-right design will reduce verification cycles, implementation iterations, and post-silicon debug time across the product
• The protocols and low power techniques you implement will directly influence power, performance, and area outcomes in customer chips
• Your collaboration with cross-functional teams will set the standard for how design, verification, and implementation work together on complex projects
• The design practices and methodologies you bring will influence how the team approaches architecture, coding standards, and release quality
• Your ability to drive projects to completion will unlock new IP releases and product milestones that depend on subsystem readiness

Requirements

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or equivalent technical field
• 8+ years of hands-on RTL design experience with multiple tape-outs under your belt, ideally in complex IP, subsystems, or SoC blocks
• Deep proficiency with Verilog or SystemVerilog and proven ability to write synthesizable, timing-clean, low power RTL at scale
• Strong working knowledge of standard protocols such as PCIe, DDR, UFS, USB, or AMBA (AXI, AHB, APB)
• Hands-on experience with low power design techniques including clock gating, power gating, retention, UPF, and multi-voltage domain architecture
• Solid understanding of logic synthesis, constraint development (SDC), static timing analysis (STA), and equivalence checking flows
• Familiarity with DFT concepts including scan insertion, ATPG, MBIST, and how testability requirements shape design architecture, experience working directly with DFT teams is a plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: In addition to company holidays, we have ETO and FTO Programs
• Family support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: Save for your future with our retirement plans that vary by region and country
• Competitive salaries