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From the employer's careers site First seen 25 Oct 2026 · Still live on 31 Oct 2026

ASIC DFT STA Engineer

Cisco San Jose, California senior full-time

Salary

$167,700 - $245,200 per year

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Description

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Minimum Qualifications:

  • Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience.
  • Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.
  • Prior working experience in timing constraint development and verification.
  • Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

Preferred Qualifications:

  • Masters degree + 10 years of relevant experience.
  • Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints.
  • Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
  • Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime.
  • Prior working experience with synthesis tools: Synopsys Fusion/design Compiler.
  • Prior working experience with Tessent tool like DFT insertion in RTL.

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Skills

Required

  • RTL design
  • CDC/RDC
  • conformal verification
  • SDC development
  • timing constraint development
  • verification
  • Perl
  • TCL
  • Python
  • Makefile

Nice to have

  • PCIE timing constraints
  • TSMC memory timing constraints
  • DFT modes
  • SDC debugging
  • STA tools
  • Synopsys TCM/Primetime
  • synthesis tools
  • Tessent tool

Ready to apply?

You apply with the employer directly. Their original posting is here: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-STA-Engineer_2027715

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