Senior Hardware Architect

We are seeking a Senior Hardware Architect for our Tegra System-on-Chips (SoC) focused on Reliability, Availability, and Serviceability (RAS).

As a Senior Hardware Architect, you will define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.

Key responsibilities:

• Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
• Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
• Work closely with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
• Understand the broader SoC architecture and identify how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
• Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models in SystemC, C/C++, Python, or other relevant modeling environments where applicable.
• Plan and review verification and validation strategies for RAS mechanisms, including error injection, recovery validation, coverage analysis, resiliency modeling, and architecture reviews.
• Assist in failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures.
• Apply RAS architecture principles to high-reliability deployment environments, including space-aware and radiation-aware use cases.

Requirements:

• MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
• At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
• Strong understanding of Reliability, Availability, and Serviceability (RAS) in the SoC context.
• Experience defining and driving hardware architecture features through the full development lifecycle.
• Strong understanding of overall SoC architecture and the ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases.

Nice to have:

• Demonstrated history of architecting and delivering complex SoC RAS features across design, verification, validation, and production phases.
• Deep familiarity with architectural resiliency techniques such as ECC, parity, redundancy, replay, checkpoint/restart, scrubbing, isolation, containment, telemetry, error logging, recovery flows, and graceful degradation.
• Experience with debug of hardware failures in simulation, emulation, post-silicon validation, production, customer deployments, or other high-reliability systems.
• Familiarity with Design for Debug, Design for Test, Design for Reliability, silicon observability, fault-injection methodology, and coverage driven validation flows.

We offer a competitive salary ranging from 184,000 USD to 356,500 USD, depending on experience and location, as well as equity and benefits.