Senior ASIC Design Efficiency Engineer

NVIDIA is seeking a Senior ASIC Design Efficiency Engineer to join our team in Santa Clara, CA, or Durham, NC. As an NVIDIAN, you'll work in an inclusive environment driving innovation in computer graphics, PC gaming, and AI computing.

The Senior ASIC Design Efficiency Engineer will focus on designing hardware accelerators and processors for next-generation mobile, embedded, and datacenter platforms. You'll develop methodologies and infrastructure to improve Performance, Power, and Area (PPA).

Key Responsibilities:

• Understand design and implementation to drive PPA improvements
• Use internal tools and industry-standard power analysis tools to enhance product power efficiency
• Develop innovative memory subsystem designs for state-of-the-art performance and power efficiency
• Collaborate with architects, designers, verification, and VLSI teams to create top-performing GPUs

Requirements:

• BS Degree in Computer Engineering, Electrical Engineering, Computer Science, or equivalent experience
• 5+ years of relevant industry experience
• Working knowledge of computer architecture fundamentals and constructs in Verilog/System Verilog
• Strong interpersonal skills for teamwork in a diverse product-oriented team

Preferred Qualifications:

• Strong analytical thought process and outstanding debug skills
• Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks
• Infrastructure development and use of AI for design and verification
• Familiarity with RTL implementation of low-power techniques and trade-offs
• Experience debugging RTL or gate-level power anomalies

Benefits:

• Competitive salary: $136,000 - $218,500 (Level 3) or $168,000 - $264,500 (Level 4)
• Equity and comprehensive benefits package
• Visit www.nvidiabenefits.com/ for more information