Description
You will work as a Principal Verification Engineer, AI-Enabled Flows at Synopsys, leading the development of verification flows that power digital IP used across the semiconductor industry.
Your role involves designing and implementing AI-enabled verification flows using VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs. You will contribute to the internal Agentic AI platform used by IP engineering teams and define verification methods, best practices, and practical AI use cases for digital IP projects.
Key responsibilities include:
- Designing and implementing AI-enabled verification flows for Synopsys digital IP
- Contributing to the internal Agentic AI platform
- Defining and documenting verification methods and best practices
- Providing technical guidance on UVM, SystemVerilog, flow optimization, and debug
- Owning technical initiatives from concept through production deployment
- Collaborating with EDA development teams to improve verification workflows
The impact of your work will be significant, as your verification flows will directly improve the quality, efficiency, and time to market for digital IP used across the semiconductor industry. Your AI-enabled methods will accelerate verification workflows for engineering teams globally, reducing manual effort and catching issues earlier.
Requirements include:
- 10+ years of hands-on IP or SoC verification experience
- Strong working knowledge of digital verification methods and Synopsys tools
- Proficiency in SystemVerilog, UVM, Tcl, and Python
- Bachelor's degree in Electrical, Electronics, or Computer Engineering
- Demonstrated ability to architect verification flows and infrastructure for complex digital designs
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
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