Principal ASIC Design Engineer

We are seeking a Principal ASIC Design Engineer to join our team. As a Hybrid role, you will work on average 2 days per week from an HPE office.

As a Principal ASIC Design Engineer, you will architect complex modules and subsystems used in high-performance networking chips. You will write detailed functional and micro-architecture specifications for your module, implement the design using Verilog or System Verilog, and ensure that your module meets power targets by using state-of-the-art power reduction techniques.

Responsibilities:

• Architect complex modules and subsystems used in high-performance networking chips
• Write detailed functional and micro-architecture specifications for your module
• Implement the design using Verilog or System Verilog
• Write functional coverage/SVA to help verification catch corner case bugs
• Ensure that your module meets power targets by using state-of-the-art power reduction techniques
• Work with Physical design team for timing closure
• Collaborate with the Verification team to validate your block
• Provide guidance to new college-grad/junior engineers and interns

Recommended skills:

• Bachelor's degree in Electrical Engineering required (Master's strongly desired) with 15+ years of relevant experience
• Strong analytical/problem-solving skills
• Demonstrated skills in leading and implementing high-performance subsystems from specification to final netlist
• Knowledge of Computer Architecture/networking protocols through prior work is strongly desired
• Strong coding skills in Verilog/System Verilog through previous work experience are necessary
• Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired
• Excellent written and verbal communications skills are necessary
• Knowledge of Perl/Python is strongly desired

We offer a comprehensive suite of benefits that supports the physical, financial, and emotional wellbeing of our team members and their loved ones.