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From the employer's careers site First seen 14 Nov 2026

ASIC Digital Verification Engineer: Ethernet / UFS / UniPro / USB (IP Verification)

Synopsys Bengaluru, Karnataka On-site mid full-time

The employer hasn't listed a salary.

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Description

The Synopsys Digital IP R&D team is hiring experienced ASIC/IP Verification Engineers (2 to 5 years) to work on advanced connectivity protocols, including Ethernet / UFS / UniPro / USB / MPhy, across commercial, enterprise, and automotive applications.

You will be part of the Synopsys IP Verification R&D team at our Bangalore R&D Center, working closely with the RTL design team within a global team of expert Verification Engineers. You will contribute to end-to-end verification of subsystems with high-speed interconnect IPs, including one or more of controllers and Phy IP related to protocols such as Ethernet / UFS / UniPro / USB / MPhy, from test planning to coverage closure and sign-off.

Key responsibilities include:

  • Developing and using state-of-the-art verification environments for the Synopsys IP family of synthesizable cores
  • Performing verification tasks on these IP cores
  • Understanding compliance testing standards and building simulation-based compliance test suites
  • Developing SystemVerilog/Verilog testbenches and test cases
  • Running regressions, analyzing coverage, and debugging failures using methodologies such as UVM and formal verification
  • Covering test planning, unit-level and system-level test environment coding, test case coding and debugging
  • Controller-PHY IP interoperability testing and regression management
  • Working with frontier AI models and building agentic workflows for verification

Requirements:

  • Engineering degree / Post graduation (B.Tech / M.Tech) with 2–5 years of verification experience
  • Hands-on experience with coding in Verilog, System Verilog and methodology such as UVM
  • Controller–PHY integration / interoperability simulation experience is a strong plus
  • Prior experience in usage of industry standard VIP is a definite advantage
  • Experience with SVA assertions, functional coverage, and coverage-driven verification
  • Strong debug skills using Verdi
  • Proficiency in one or more structured programming languages such as C, C++, Python
  • Experience building AI agents, agentic workflows, and AI-driven engineering automation will be a distinct advantage

Benefits:

  • Comprehensive medical and healthcare plans
  • Time away programs
  • Family support
  • ESPP
  • Retirement plans
  • Competitive salaries

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Skills

Required

  • Verilog
  • System Verilog
  • UVM
  • SVA assertions
  • functional coverage
  • coverage-driven verification
  • C
  • C++
  • Python

Nice to have

  • Controller–PHY integration / interoperability simulation
  • industry standard VIP
  • AI agents
  • agentic workflows
  • AI-driven engineering automation
Apply on Synopsys