Description
The Synopsys Digital IP R&D team is hiring experienced ASIC/IP Verification Engineers (2 to 5 years) to work on advanced connectivity protocols, including Ethernet / UFS / UniPro / USB / MPhy, across commercial, enterprise, and automotive applications.
You will be part of the Synopsys IP Verification R&D team at our Bangalore R&D Center, working closely with the RTL design team within a global team of expert Verification Engineers. Your responsibilities will include:
- Contributing to end-to-end verification of subsystems with high-speed interconnect IPs, including one or more of controllers and Phy IP related to protocols such as Ethernet / UFS / UniPro / USB / MPhy, from test planning to coverage closure and sign-off
- Developing and using state-of-the-art verification environments for the Synopsys IP family of synthesizable cores, and performing verification tasks on these IP cores
- Understanding compliance testing standards and building simulation-based compliance test suites
- Developing SystemVerilog/Verilog testbenches and test cases; running regressions, analyzing coverage, and debugging failures using methodologies such as UVM and formal verification
- Covering test planning, unit-level and system-level test environment coding, test case coding and debugging, Controller-PHY IP interoperability testing, and regression management
- Working with frontier AI models and building agentic workflows for verification, from automated testbench creation and test planning to coverage analysis and closure
- Contributing to IP development used in high-performance computing, communications, servers, consumer devices, and automotive applications that power the technologies of tomorrow
- Collaborating across design, architecture, and validation teams and driving issues to resolution
Requirements:
- Engineering degree / Post graduation (B.Tech / M.Tech) with 2–5 years of verification experience
- Hands-on experience with coding in Verilog, System Verilog and methodology such as UVM
- Controller–PHY integration / interoperability simulation experience is a strong plus
- Prior experience in usage of industry standard VIP is a definite advantage
- Experience with SVA assertions, functional coverage, and coverage-driven verification
- Strong debug skills using Verdi (waveform + transaction/protocol-level analysis, RCA)
- Proficiency in one or more structured programming languages such as C, C++, Python
- Experience building AI agents, agentic workflows, and AI-driven engineering automation will be a distinct advantage
- Strong analytical thinking, problem-solving ability, debugging skills, and attention to detail
- Ability to collaborate across design/architecture/validation teams and drive issues to resolution
- Effective written and oral communication is a must; Good interpersonal skills for working in a geographically distributed team
- High levels of motivation, curiosity, and a self-driven approach to learning
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family
- In addition to company holidays, we have ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
- Save for your future with our retirement plans that vary by region and country
- Competitive salaries
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