ASIC Designer

The Silicon One team at Cisco is seeking an experienced ASIC designer to lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.

You will use your expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up. You will collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models, while supporting early emulation and FPGA platforms.

Minimum Qualifications:

• Bachelor’s + 8 years of related experience, or Master’s + 6 years of related experience, or PhD + 3 years of related experience
• Prior experience with microarchitectural RISC-V, ARM or ARC processor ecosystems.
• Prior experience with on-chip interconnect fabrics (such as AXI, CHI, NoC).
• Prior experience with PCIe subsystems.
• Prior experience with ASIC/SoC design flow, including RTL development using SystemVerilog, pre-silicon verification, lint, CDC/RDC, synthesis/timing/constraints, implementation handoff, and post-silicon bring-up for SoC blocks.

Preferred Qualifications:

• Prior experience in leading CPU/SoC subsystem architecture or design for high-performance networking or data-center SoCs
• Prior experience with Boot, Security, Root of Trust (RoT), secure boot chains, and debug/trace infrastructure (such as CoreSight, RISC-V Debug).

The starting salary range for this position is $186,900.00 to $267,700.00.

Benefits include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.