Description
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
As a Senior ASIC Design Engineer, you will define and architect high-performance blocks for the latest, most advanced networking ASICs. You will perform micro-architecture and logic design to deliver maximum throughput, while using minimum power. You will collaborate with the verification team in the development of the testplan and assist in debugging test failures. You will also collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes.
To be successful in this role, you need to bring:
- Strong Verilog RTL coding skills
- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
- Knowledge of high performance memory subsystems
- Knowledge of multi-domain clock synchronization and high-speed serial interfaces
- Strong problem solving and ASIC debugging skills
- Excellent written and verbal communications skills
- MSEE or BSEE is required
We offer a comprehensive suite of benefits that supports the physical, financial, and emotional wellbeing of our team members and their loved ones. We invest in your career and provide programs to help you reach your career goals. We are unconditionally inclusive and value individual uniqueness.