Description
You are a Senior Staff Digital Methodology Engineer - Design for Testability (DFT) at Synopsys, a leading provider of electronic design automation (EDA) software used in chip design, verification, and manufacturing.
As a seasoned expert in DFT, you will work on methodologies that define how the world's most complex chips get tested. You will define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs, translating architecture decisions into deployable best practices.
Your responsibilities will include:
- Leading deployment of advanced test solutions including scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation networks, and embedded test IP across multi-billion-gate designs
- Architecting scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards for complex multi-die and chiplet-based systems
- Developing automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl that accelerate adoption across business units
- Serving as technical leader and subject matter expert for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements and internal escalations
The impact you will have:
- Enabling successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs in AI, automotive, and hyperscale computing
- Driving measurable improvements in test coverage, pattern count reduction, and manufacturing yield through methodology standardization and best-practice development
- Influencing next-generation TestMAX capabilities by translating customer deployment challenges into product requirements that shape future releases
To be successful in this role, you will need:
- 10+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies
- Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs, including successful tapeouts
- Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments
- Deep technical knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, stuck-at/transition/path-delay/bridge/cell-aware fault models, and coverage optimization techniques
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including medical and healthcare plans, time away, family support, ESPP, retirement plans, and competitive salaries.