Description
This is a hybrid role with four days per week at Cisco’s Yerevan office.
The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture.
Your primary focus will be to drive high-quality Design for Test (DFT) verification, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation.
Responsibilities:
- Take part in all aspects of digital design, from micro-architecture to RTL design and qualification.
- Sub-system/SoC integration and verification.
- Review/enhance RTL codes.
- Improve flows and methodologies to streamline IP/SoC development and integration.
- Work closely with the verification team for complex debugs to resolve verification failures.
- Close interaction with physical design team to reach better physical design QoR.
Minimum Qualifications:
- 5+ years of industry experience in ASIC digital design.
- Proficient in Verilog/System Verilog coding.
- Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
- Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.
- Ability to write scripts using Python, Tcl, Make.
- Good communications skills, self-motivated and well-organized.
Preferred Qualifications:
- Familiarity with power optimization techniques, power intent (UPF), power estimation.
- Familiarity with DFT/MBIST is a plus