Description
We are seeking a Principal Signal Integrity Engineer to work with our experienced signal integrity team on high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis for cutting-edge networking product design.
Responsibilities:
- Perform COM (channel margin analysis) to provide design trade-offs amongst ASIC package, board, and connectors
- Correlate ASIC PAM4 SerDes simulation results with measurements and work with component and ASIC vendors to improve model accuracy
- Perform PCB timing analysis and work with board engineers and layout designers to implement all design SI rules
- Develop and document all layout/SI design rules and checklists
- ASIC PAM4 SerDes parametric tuning to improve design margins of serial links
- Perform SI DVT measurements on boards and correlate simulations with DVT measurements
Requirements:
- Typically 10+ years of Signal Integrity analysis experience with a bachelor's degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering
- Experience with 56G/112G ASIC PAM4 SerDes technologies is required
- Hands-on experience in serial channels up to 200G line rates for coefficient tuning, TP1A measurements
Preferred Skills:
- Proficient with CAD tools such as Ansys HFSS, SIwave ADS, Allegro, Sigrity, and MATLAB
- Proficient with lab equipment such as oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, phase noise Analyzers
- Strong capabilities to debug and provide solutions for ASIC PAM4 SerDes and channel performance issues
Benefits:
- Comprehensive suite of benefits that supports physical, financial, and emotional wellbeing
- Investment in career development and growth
- Unconditional inclusion and flexible work arrangements