Description
Cisco Common ASIC Group is seeking an experienced Senior Verification Engineer to work on next-generation switching systems. As part of the ASIC team, you will develop ASICs for switch products that drive integration with software, including OpenStack, Docker, and Open vSwitch.
Responsibilities include:
- Designing UVM/SystemVerilog testbenches
- Defining new DV methodologies
- Enhancing existing testbenches
- End-to-end verification of design blocks
- Contributing to top-level verification
- Participating in emulation testing efforts and ASIC bring-up
Requirements:
- Bachelor's or master's degree in Electrical Engineering or Computer Engineering
- 5+ years of ASIC Design Verification experience
- Hands-on experience with System Verilog and UVM methodology
- In-depth knowledge of C++, scripting, and ASIC design and verification flow
- Strong understanding of high-speed Ethernet protocols and packet processing
- Excellent written and verbal communication skills
Preferred skills:
- Python, Perl, TCL, or shell programming experience
- Familiarity with functional coverage and constrained random DV environments
- Experience with code coverage analysis and merging