Description
We are now looking for a Senior ASIC Floorplan Design Engineer!
NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic company.
Responsibilities:
- Work with architects, design leads, physical design leads and package leads to develop and craft and optimize floorplans during early chip development.
- Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
- Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
- Build tools and improve existing infrastructure to optimize chip area and speed of execution.
Requirements:
- Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
- 12+ years of relevant work experience.
- A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
- Experience in Verilog, System Verilog or similar HVL.
- Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
- Strong communication and interpersonal skills and ability & desire to work as a great teammate.
- Python, Perl and C/C++ programming language experience.
Benefits:
- Eligible for equity and benefits.