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From the employer's careers site First seen 28 Oct 2026

PCB Design Engineer – System Lead, Signal Integrity, and System Architecture (Onsite)

Cisco Milpitas, California On-site senior full-time

Salary

$194,600 to $285,700 per year

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Description

We are seeking a Senior Technical Lead Hardware Board Design Engineer to shape multi-year hardware architecture, design standards, and technical strategy for major networking products. You will lead high-impact, cross-functional initiatives, resolve complex technical problems, and influence senior leaders.

Responsibilities:

  • Define long-term hardware architecture, power-delivery strategy, design standards, and technology roadmaps for high-performance networking systems.
  • Lead major, multi-disciplinary hardware initiatives from early concept through product release and customer delivery.
  • Act as a senior escalation point for novel or high-risk architectural, signal integrity, power integrity, reliability, field, and manufacturing issues.
  • Develop and communicate technical strategies that align multiple business units and engineering disciplines.
  • Establish reusable methods, constraints, verification practices, and quality standards for board design.
  • Guide senior engineers and technical leaders through architecture reviews, design tradeoffs, and complex investigations.
  • Represent hardware engineering in executive reviews, strategic supplier discussions, standards activities, and selected external technical engagements.
  • Anticipate industry and technology shifts and recommend investments in future hardware capabilities.
  • Drive decisions using simulations, laboratory evidence, product data, and a clear understanding of business impact.

Minimum Qualifications:

  • Bachelor’s degree in Electrical Engineering or Computer Engineering and 11+ years of experience, or Master’s in Electrical Engineering or Computer Engineering and 7+ years of related experience, or PhD in Electrical Engineering or Computer Engineering and 4+ years of related experience.
  • End-to-End System Design: Experience in hardware board design and system architecture,taking products from concept through production,for high-performance systems, including PCIe, Ethernet, DDR, SerDes, and advanced thermal/EMI management.
  • Technical Validation & Tools: Experience with high-speed digital design, signal and power integrity, power distribution, and reliability testing, supported by hands-on use of Cadence design tools and advanced lab instrumentation (oscilloscopes, logic/spectrum analyzers).
  • Strategic Leadership & Delivery: Experience leading complex, multi-site, and cross-functional engineering initiatives, partnering with silicon vendors and contract manufacturers to solve high-impact, ambiguous technical challenges at scale.

Preferred Qualifications:

  • Systems Architecture: Experience with advanced networking systems, ASICs, FPGAs, high-speed memory, multi-gigabit SerDes, and advanced packaging.
  • Specialized Technologies: Experience in co-packaged/near-packaged optics, signal/power integrity budget analysis, ultra-high-speed signaling, and next-generation power delivery.
  • Technical Proficiency: Hands-on experience with Cadence (Concept/Allegro), HyperLynx, ANSYS, Keysight ADS, and advanced lab equipment (VNA, TDR, high-bandwidth oscilloscopes, protocol analyzers).
  • Automation: Experience with creating test scripts using Python to streamline validation and design tasks.
  • Problem-Solving: Analytical, methodical approach to decomposing complex issues, evaluating empirical evidence, and documenting clear, actionable conclusions.
  • Collaboration: History of working effectively within cross-functional teams to drive initiatives forward.
  • Leadership & Influence: History of influencing senior technical and business leaders across organisational boundaries, underpinned by exceptional written, verbal, and executive-level communication skills. Dedicated to driving excellence through the mentorship of senior engineering talent.
  • Innovation & Industry Impact: A record of delivering large-scale products and technical innovations, evidenced by a history of patents, influential publications, and active standards participation. Committed to advancing the field through strategic thought leadership.

Benefits:

  • Medical, dental and vision insurance
  • 401(k) plan with a Cisco matching contribution
  • Paid parental leave
  • Short and long-term disability coverage
  • Basic life insurance
  • 10 paid holidays per full calendar year
  • 1 paid day off for employee’s birthday
  • Paid year-end holiday shutdown
  • 4 paid days off for personal wellness
  • 16 days of paid vacation time per full calendar year (non-exempt employees)
  • Flexible vacation time off program (exempt employees)
  • 80 hours of sick time off provided on hire date and each January 1st thereafter
  • Optional 10 paid days per full calendar year to volunteer

Skills

Required

Nice to have

  • Systems Architecture
  • ASICs
  • FPGAs
  • High-speed memory
  • Multi-gigabit SerDes
  • Advanced packaging
  • Co-packaged/near-packaged optics
  • Signal/power integrity budget analysis
  • Ultra-high-speed signaling
  • Next-generation power delivery
  • Python
  • Automation
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