SerDes IP's Applications Engineering, Sr Staff Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You are a highly motivated, customer-focused engineering professional with a passion for enabling next-generation semiconductor solutions. You thrive in dynamic, collaborative environments and are energized by solving complex technical challenges.

What You'll Be Doing:

• Provide technical guidance and hands-on support to customers integrating Synopsys Interface IP into their ASIC SoC/systems.
• Conduct detailed integration reviews and troubleshoot complex integration challenges throughout the SoC design flow.
• Collaborate with customers to resolve technical issues related to RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring-up.
• Support silicon bring-up and characterization in system environments.
• Document best practices, develop application notes, and deliver training to enable customer success with Synopsys solutions.
• Participate in cross-functional teams to relay customer feedback and contribute to product improvements.

The Impact You Will Have:

• Accelerate customer product development cycles by ensuring seamless integration of Synopsys Interface IP into complex SoC designs.
• Drive customer success and satisfaction, resulting in repeat business and long-term partnerships.
• Enhance the quality and reliability of customer silicon by identifying and resolving integration and bring-up challenges.
• Influence the evolution of Synopsys IP products and solutions through direct feedback and collaboration with R&D teams.

What You'll Need:

• Master's degree with 10+ years of industry experience or equivalent.
• At least 10+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles.
• Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure.
• Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, USB, SATA.
• Proficient in RTL and gate-level simulation debugging, with familiarity in front-end tools like Design Compiler, Fusion Compiler, and PrimeTime.
• Experience with silicon bring-up and system-level characterization in lab environments.
• Domain knowledge of PCI Express implementation flows and specification.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.