ASIC Digital Design, Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.

You are an early-career engineer ready to make your mark in semiconductor design.

What You'll Be Doing

• Learn the latest formal verification methodology from experts and apply your learnings to live projects.
• Work with a team of seasoned FV engineers and execute validation as per defined plans.
• Support quality improvements and contribute insights that help enhance verification tool capabilities.
• Write and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.
• Script verification flows using Python, Perl, or Tcl to automate repetitive tasks and improve team productivity in Unix/Linux environments.

The Impact You Will Have

• Help catch critical design bugs before tapeout that would otherwise cost months and millions to fix in silicon.
• Contribute to the quality and reliability of Synopsys IP and EDA tools that power semiconductor development across the industry.
• Accelerate verification closure on complex designs by applying formal methods that simulation alone cannot cover.
• Strengthen the formal verification methodology at Synopsys by bringing fresh perspectives and identifying gaps in existing flows.

What You'll Need

• Bachelors or Master’s degree in Electronics, Electrical, Instrumentation, or a related engineering discipline
• 0 to 2 years of experience in digital design, verification, or related semiconductor work (internships, projects, and coursework count).
• Strong understanding of computer architecture and digital design fundamentals including state machines, pipelining, and timing.
• Hands-on experience with hardware description languages, Verilog or SystemVerilog preferred.
• Proficiency in at least one scripting language such as Python, Perl, or Tcl, and comfort working in Unix or Linux environments.
• Solid academic performance with relevant coursework or project work in VLSI, digital design, or verification.
• Experience with formal verification tools, assertion languages, or model checking is a strong plus.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.