DDR/LPDDR IP Design Principal Engineer

We are seeking a highly motivated and innovative senior engineer with wide-spectrum knowledge of generic ASIC design methodology, and simulation/silicon debug skills.

The successful candidate will work as part of a highly experienced DDR/LPDDR design and verification team, targeting current and next-generation technology. A theoretical and practical background in DDR or LPDDR is a solid plus.

Key Responsibilities

• Work on digital design based on predefined RTL coding style, including Verilog and System Verilog, clean RTL check violations in lint, CDC, DFT, and synthesis
• Solid debugging skills and ability to root cause issues, including both simulation and silicon
• Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality
• Good communication skills for interacting between different design groups and customer support teams

Preferred Qualifications

• Strong desire to learn and explore new technologies
• Demonstrates good analysis and problem-solving skills
• Knowledge in interface technologies such as DDR, HBM, UCIe is a plus
• Scripting experience in Shell, Perl, Python, and TCL is a plus
• Knowledge of analogic circuit is a plus
• Interacting with Application Engineers for customer support

Benefits

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
• ESPP: purchase Synopsys common stock at a 15% discount
• Retirement plans that vary by region and country
• Competitive salaries