Principal ASIC Verification Engineer - DDR/LPDDR

You are a seasoned verification engineer with a passion for leading teams and developing cutting-edge semiconductor solutions. As a Principal ASIC Verification Engineer - DDR/LPDDR at Synopsys, you will lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff. You will work on DesignWare IP that powers real products, with a team that takes verification as seriously as you do.

Key Responsibilities:

• Lead a team of verification engineers through full IP verification cycles
• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores
• Define test plans that cover corner cases, protocol compliance, and system-level interactions
• Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers
• Extract, analyze, and drive functional coverage and code coverage metrics to closure

Requirements:

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 8+ years of hands-on verification experience
• Proven track record leading verification teams through IP project delivery
• Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow
• Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries