Description
The Common Hardware Group at Cisco is seeking an experienced ASIC DFT Engineer to work on designing, developing, and testing complex ASICs. You will be responsible for implementing Hardware Design-for-Test (DFT) features, developing innovative DFT IP, and collaborating with multi-functional teams.
Key Responsibilities:
- Implement DFT features that support ATE, in-system test, debug, and diagnostics needs
- Develop innovative DFT IP in collaboration with teams and play a key role in full chip design integration
- Work closely with design, verification, and PD teams to enable integration and validation of Test logic
- Craft solutions and debug with minimal mentorship
Requirements:
- Bachelor's or Master's Degree in Electrical or Computer Engineering
- 4-8 years of experience in ASIC design for test hardware engineering
- Knowledge of DFT, test, and silicon engineering
- Experience with JTAG protocols, Scan insertion, ATPG, BScan, and EDA tools like TestMax, Tetramax, Tessent
- Gate level simulation, debugging with VCS and other simulators
- Post-silicon validation and debug experience
- Strong verbal skills and ability to thrive in a multifaceted environment
- Scripting skills in Tcl, Python/Perl
Preferred Qualifications:
- Test Static Timing Analysis
- Post silicon validation using DFT patterns
What We Offer:
- Opportunities to grow and build in a global network of doers and experts
- Collaborative environment with empathy to make big things happen
- Innovative solutions that power how humans and technology work together