Description
As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, including synthesis, formal verification, constraints definition, timing closure/sign off, and study on the timing impact of process and related methodology work.
Responsibilities:
- Chip integration and netlist generation
- Synthesis
- RTL/netlist quality check
- Formal Verification
- Constraints creation and validation, timing budget
- Work with ASIC team to analyze/resolve special timing issues
- Cross-Team collaboration to implement chip partitioning and floorplan
- Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level
- Achieve special mode timing closure, such as io, test, clock, async etc.
- Function eco creation
- Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)
- Flow automation development for above areas
- Methodology in any of above areas
Requirements:
- MS in EE or Microelectronics (or equivalent experience)
- Project experience in IC design implementation
- Courses taken in circuit design, digital design
- Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful
- Proficient user of Python or TCL is helpful
- Proficient in English reading and writing