Description
The Common Hardware Group at Cisco is seeking a Technical Leader to own and drive end-to-end DFT flow architecture. You will build and maintain scalable CAD infrastructure, spearhead the development of robust regression frameworks, and leverage AI-driven automation to enhance log analysis and debug processes.
Responsibilities:
- Build and maintain scalable CAD infrastructure that spans the entire design cycle from RTL and insertion to ATPG, simulation, and reporting
- Spearhead the development of robust, LSF-based regression frameworks
- Leverage AI-driven automation to enhance log analysis, failure triage, and intelligent debug processes
- Collaborate cross-functionally with RTL, Physical Design, and Validation teams to ensure seamless integration and signoff
- Establish standardized, high-reusability flows that enforce best practices
Minimum Qualifications:
- 8+ years of experience in CAD or test automation for semiconductor designs
- Experience applying AI/ML techniques to EDA workflows
- Prior experience with EDA DFT toolchain like Synopsys TestMAX, Synopsys VCS, Siemen's Tessent
- Experience in Tcl, Python, Perl, and shell scripting
- Experience building automated flows and regression systems in compute farm environments
- Prior experience with SoC integration and cross-functional workflows
Preferred Qualifications:
- Familiarity with data analytics tools
- Experience with large-scale regression systems and distributed job management
- Exposure to ATE/tester formats and silicon bring-up/debug
Benefits:
- Medical, dental, and vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short and long-term disability coverage
- Basic life insurance
- Paid time away
- Optional 10 paid days per year to volunteer
Salary Range: $186,900.00 - $267,700.00