Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

You will verify Interface IP that powers the semiconductor industry's most critical applications, focusing on PCIe, CXL, DDR, and Ethernet protocols.

Key Responsibilities:

• Own end-to-end verification of Interface IP blocks
• Build and evolve UVM-based verification environments
• Define verification strategies and test plans
• Develop constrained-random, coverage-driven test scenarios
• Debug complex multi-layer issues
• Collaborate with architecture, design, firmware, and systems teams
• Mentor verification engineers on UVM methodology and best practices

Requirements:

• Bachelor's or Master's in Electrical Engineering or Computer Engineering
• 8+ years of hands-on ASIC or SoC verification experience
• Deep expertise in SystemVerilog and UVM methodology
• Strong protocol knowledge in PCIe, CXL, DDR, or Ethernet
• Proven experience developing constrained-random and coverage-driven verification solutions

Benefits:

• Comprehensive medical and healthcare plans
• Time away programs
• Family support
• ESPP
• Retirement plans
• Competitive salaries