Sr Staff Product Engineer, Simulation and Mixed-Signal Verification

You are a seasoned Sr Staff Product Engineer with expertise in simulation and mixed-signal verification, looking to engineer the future with us at Synopsys.

As a leader in engineering solutions from silicon to systems, Synopsys enables customers to rapidly innovate AI-powered products. You will work with semiconductor teams building chips that power AI, automotive, mobile, and networking systems.

Responsibilities

• Lead technical engagements with strategic customers deploying simulation and verification solutions for complex SoCs

• Drive resolution of challenging issues involving RTL and gate-level simulation, testbench integration, assertion failures, and more

• Optimize simulation performance and regression throughput

• Support analog mixed-signal verification, including digital-analog co-simulation and behavioral modeling

• Collaborate with Product Management and R&D to define requirements and influence the roadmap

• Develop and deliver technical presentations, training sessions, and workshops

• Create application notes, reference flows, and debug playbooks

The Impact You Will Have

• Enable semiconductor companies to verify and tape out SoCs that power AI accelerators, automotive systems, and more

• Reduce time-to-tapeout by resolving simulation bottlenecks and verification signoff blockers

• Influence the evolution of Synopsys simulation tools

• Scale verification methodologies across customer organizations

• Accelerate adoption of advanced verification techniques

• Mentor applications engineers and customer verification teams

• Drive customer success metrics that directly affect Synopsys revenue

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline

• 5+ years in Product Engineering, Applications Engineering, Functional Verification, or Simulation Technologies

• Deep expertise in RTL and gate-level simulation, SystemVerilog, UVM, and simulation compilation

• Strong understanding of event-driven simulation semantics, X-propagation, and timing simulation

• Proven ability to debug complex SoC verification environments

• Experience with analog mixed-signal verification is a strong plus

• Strong customer engagement skills

Who You Are

• Comfortable walking into a customer war room and proposing a path forward

• Fluent in reading SystemVerilog and UVM code

• Able to explain complex simulation concepts clearly

• Proactive in finding and implementing workarounds

• Able to manage multiple customer engagements simultaneously